-------------------------------------------------------------------------------
-- Description: This is the testbench that instantiates the arithmetic unit and provides
-- the input signals. The outputs can be checked on the simulation waveforms.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity tb_Register is
end tb_Register;

architecture structural of tb_Register is
	component register_update
		port(Input     : in  STD_LOGIC_VECTOR(7 downto 0);
			 RegCtrl   : in  STD_LOGIC_VECTOR(1 downto 0);
			 next_RegA : out STD_LOGIC_VECTOR(7 downto 0);
			 next_RegB : out STD_LOGIC_VECTOR(7 downto 0));
	end component register_update;
	
	signal RegA : STD_LOGIC_VECTOR(7 downto 0);
	signal RegB : STD_LOGIC_VECTOR(7 downto 0);
	signal Input : STD_LOGIC_VECTOR(7 downto 0);
	signal RegCtrl : STD_LOGIC_VECTOR(1 downto 0);
	constant period : time := 25 ns;
	signal next_RegB : STD_LOGIC_VECTOR(7 downto 0);
	signal next_RegA : STD_LOGIC_VECTOR(7 downto 0);
	
	
begin                                   -- structural

Input <= "00000001" ,
"00000010" after period,
"00000001" after 2*period,
"00000010" after 3*period,
"00000001" after 4*period,
"00000010" after 5*period,
"00000001" after 6*period,
"00000010" after 7*period,
"00000001" after 8*period,
"00000010" after 9*period,
"00000001" after 10*period;

RegCtrl <= "00", 
"01" after period,
"10" after 2*period,
"01" after 3*period,
"10" after 4*period,
"01" after 5*period,
"10" after 6*period,
"01" after 7*period,
"10" after 8*period,
"00" after 9*period,
"11" after 10*period;

DUT: register_update
	port map(
		Input     => Input,
		RegCtrl   => RegCtrl,
		next_RegA => next_RegA,
		next_RegB => next_RegB
	);	

end structural;
